ordering number : enn * 6327 21800rm (ot) no. 6237-1/7 overview the LC85050 is a cordless answering machine system ic that integrates an extensive set of functions on a single chip. these functions include a dsp that provides audio recording and playback functions, voice recognition functions, text-to-speech synthesis, and line and audio echo cancellation, a ? a/d converter, a ? d/a converter, a flash memory interface, and a host cpu interface. the LC85050 uses the pulcod tm (pulse code excited linear prediction) high-compression ratio compression algorithm to allow up to 19 minutes of audio recording on 4m of external flash memory. furthermore, the optional ld-adpcm (low-distortion adpcm) waveform encoding algorithm allows the recording and playback of high-quality audio signals. the LC85050? line and audio echo cancellation function allows it to implement a speakerphone function for answering machine/telephone products. it also includes itu-t v.23 and bell 202 conforming data transmission and reception functions to support caller id. the LC85050? text-to-speech synthesis function allows end products to announce the name of the calling party. its speaker-independent voice recognition function can be used to allow users to easily enter telephone numbers in its phone book. the LC85050? speaker-dependent voice recognition function allows users to pre-register the names of people to call with the user? own voice. then the user can then either recall any of those parties?phone number, or even call the person, simply by speaking the name. furthermore, the LC85050 can easily implement all of the functions required by standard telephone or answering machine products, including dtmf and other tone generation and detection as well as music synthesis. features pulcod tm (high compression ratio encoding) ?igh compression ratio: 3.6 kbps ?utomatic input gain adjustment function ?oice trigger function ?ilence removal function ?ail cut function ?ariable-speed playback function preliminary LC85050 sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan cordless answering machine system ic cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. continued on next page. 0.15 1.6 14.0 17.2 0.8 124 25 40 41 64 65 80 21.6 0.8 3.0max 1.0 2.7 15.6 0.8 1.6 0.35 23.2 20.0 0.8 0.8 sanyo: qfp80e (qip80e) [LC85050] package dimensions unit: mm 3174-qip80e
ld-adpcm function (waveform encoding) (optional function) ?ompression ratio: 14.4, 21.6, and 28.8 kbps ?utomatic input gain adjustment function ?oice trigger function ?ail cut function text-to-speech synthesis function ?ccent adjustment ?atakana input voice recognition function ?peaker-independent recognition (15 words) ?peaker-dependent recognition (50 words) flash memory management function (8m address space) ?lash memory: 4 m ( 1 or 8) full-duplex hands-free function ?ine echo canceler ?udio echo canceler for speakerphone operation telephone conversation recording using ld-adpcm (option) ?tmf detection ?aller id detection modem functions ?ell 202 (1200 bps) send/receive ?tu-t v.23 (1200 bps) send/receive ?ynchronous/asynchronous communication functions start/stop synchronization, hdlc, ddi, and ntt support ?rogrammable reception sensitivity (?0 dbm to ?7 dbm) programmable tone generation and detection ?ndividually adjustable reception sensitivity (?0 dbm to ?7 dbm) dtmf generation and detection call progress tone detection ?djustable reception sensitivity (?0 dbm to ?7 dbm) melody function (option) programmable transmission level (0 dbm to ?5 dbm) reception dynamic range: 0 to ?7 dbm self-diagnostic function monitor output function host cpu interface ?-wire serial interface (clock synchronous) ?-bit parallel interface output ports (up to 12 ports): 3 output ports are always available. low-power cmos supply voltage ?ingle 3.3 v supply, or dual 3.3 and 5.0 v supply voltages package: qip-80e no. 6237-2/7 LC85050 continued from preceding page. parameter symbol conditions ratings unit maximum supply voltage v dd 3 ?.3 to +4.2 v v dd 5 ?.3 to +6.0 v i/o voltages v i 3, v o 3 ?.3 to v dd 3 + 0.3 v v i 5, v o 5 ?.3 to v dd 5 + 0.3 v allowable power dissipation pdmax ta 25? 500 mw operating temperature topr ?0 to +70 ? storage temperature tstg ?5 to +125 ? soldering conditions hand soldering 3 seconds 350 ? reflow soldering 10 seconds 235 ? specifications absolute maximum ratings at ta = 25?, gnd = 0 v parameter symbol conditions ratings unit min typ max supply voltage v dd 3 3.0 3.3 3.6 v v dd 5 3.0 5.0 5.5 v input voltage range v in 30v dd 3v v in 50v dd 5v allowable operating ranges at ta = ?0 to +70?, gnd = 0 v applicable pins v i 3, v o 3, v in 3: plli, pllo, rin, auxo, auxi, spout, mic, vref, txa, rxa v i 5, v o 5, v in 5: all pins other than the above.
no. 6237-3/7 LC85050 parameter symbol conditions ratings unit min typ max input high-level voltage v ih 1 cmos (1), (4) 0.7 v dd 5v v ih 2 cmos schmitt inputs (2) 0.8 v dd 5v input low-level voltage v il 1 cmos (1), (4) 0.3 v dd 5v v il 2 cmos schmitt inputs (2) 0.2 v dd 5v output high-level voltage v oh i oh = ? ma (3), (4) v dd 5 ?2.1 v output low-level voltage v ol i ol = 4 ma (3), (4) 0.4 v input leakage current i il v i = gnd, v dd 5 ?0 +10 ? output leakage current i oz in the high-impedance output state ?0 +10 ? oscillator frequency f clk 3.6864 mhz current drain i dd 1 operating 110 150 ma i dd 1 in power down mode 5 a dc characteristics (1) at ta = ?0 to +70?, gnd = 0 v, v dd 5 = 4.5 to 5.5 v, v dd 3 = 3.0 to 3.6 v the applicable pins are as follows. (1) tester, testen, testd, ps, xin, rb1, rb0 (2) reset, cpucs, cpuoe, cpuwe (3) busy, ireq, plock, pa0 to pa2, mcs0, mcs1, mwe, mre, cle, ale, wp0, wp1, eyeclk, eyesync, eyed, xout (4) cd0 to cd7, md0 to md7 note: the plli, pllo, rin, auxo, auxi, spout, mic, vref, rxa, and txa pins are not included in the dc characteristics ratings. parameter symbol conditions ratings unit min typ max input high-level voltage v ih 1 cmos (1), (4) 0.7 v dd 5v v ih 2 cmos schmitt inputs (2) 0.75 v dd 5v input low-level voltage v il 1 cmos (1), (4) 0.2 v dd 5v v il 2 cmos schmitt inputs (2) 0.15 v dd 5v output high-level voltage v oh i oh = ? ma (3), (4) v dd 5 ?0.8 v output low-level voltage v ol i ol = 2 ma (3), (4) 0.4 v input leakage current i il v i = gnd, v dd 5 ?0 +10 ? output leakage current i oz in the high-impedance output state ?0 +10 ? oscillator frequency f clk 3.6864 mhz current drain i dd 1 operating 100 140 ma i dd 1 in power down mode 5 a dc characteristics (2) at ta = ?0 to +70?, gnd = 0 v, v dd 5 = 3.0 to 3.6 v, v dd 3 = 3.0 to 3.6 v
system block diagram the diagram below shows a circuit that uses serial mode for the host cpu interface. no. 6237-4/7 LC85050 +3.3vd rin txa rxa verf mic spout axui axuo dv dd 5 dv dd 3 dgnd pv dd pgnd av dd agnd testr testen testd dsp (favor-11) pllo plli plock reset xin xout din dout dck dset cs busy ireq p/s md0/mdi md1/mdo mcs0 mcs1 sk/mre r/b0 r/b1 wp0 wp1 pa 0 pa 1 pa 2 mwe/pa3 ale/pa4 cle/pa5 md2/pa6 md3/pa7 md4/pa8 md5/pa9 md6/pa10 ma7/pa11 pll frequency multiplier timing generator host cpu interface memory interface d/a converter a/d converter reference voltage supply a/d converter d/a converter a/d converter d/a converter hybrid circuit power supply test circuit monitor output circuit telephone line microphone speaker auxiliary analog input auxiliary analog output
no. 6237-5/7 LC85050 pin functions type i input b bidirectional nc not connected o output p power supply pin no. pin i/o function 1pv dd p pll frequency multiplier 3.3 v power supply 2 pgnd p pll frequency multiplier ground 3 rin i pll frequency multiplier bias input 4 plli i pll frequency multiplier vco input 5 pllo o pll frequency multiplier charge pump output 6 plock o pll frequency multiplier operating status output 7 testr i 8 testen i test inputs. these input must be connected to dgnd during normal operation. 9 testd i 10 reset i reset input 11 xin i oscillator amplifier input (3.6864 mhz) 12 xout o oscillator amplifier output 13 dgnd p digital system ground 14 dv dd 3 p digital system 3.3 v power supply 15 p/s i host cpu interface selection signal 16 cpucs i host cpu chip select signal 17 cpuoe/dck i in parallel mode: host cpu read signal in serial mode: data clock input signal 18 cpuwe/dset i in parallel mode: host cpu write signal in serial mode: data transfer complete input 19 cd0/din b in parallel mode: host cpu data bus lines 20 cd1/dout b in serial mode: cd0 functions as host cpu serial data signal, 21 cd2 b and cd1 functions as the host cpu serial data output. 22 cd3 b 23 dgnd p digital system ground 24 dv dd 5 p digital system 5.0 v power supply 25 cd4 b 26 cd5 b in parallel mode: host cpu data bus lines 27 cd6 b 28 cd7 b 29 busy o status output that indicates the host cpu interface status 30 ireq o interrupt request output 31 dv dd 3 p digital system 3.3 v power supply 32 dgnd p digital system ground 33 nc 34 nc 35 nc 36 pa0 o 37 pa1 o output ports 38 pa2 o 39 dv dd 5 p digital system 5.0 v power supply 40 dgnd p digital system ground 41 av dd p analog system 3.3 v power supply 42 agnd p analog system ground 43 auxi i auxiliary analog input 44 mic i analog audio input 45 rxa i analog circuit input 46 vref o analog reference output 47 auxo o auxiliary analog output 48 spout o analog audio output 49 txa o analog circuit output 50 agnd p analog system ground continued on next page.
no. 6237-6/7 LC85050 continued from preceding page. pin no. pin i/o function 51 av dd p analog system 3.3 v power supply 52 dgnd p digital system ground 53 dv dd 3 p digital system 3.3 v power supply 54 eyed o monitor data output 55 eyesync o monitor sync signal output 56 sysclk o monitor clock output 57 wp1 o audio memory write protect output 58 r/b1 i status input that monitors audio memory 59 md0/mdi b parallel type: audio memory data bus line serial type: audio data input 60 md1/mdo b parallel type: audio memory data bus line serial type: audio data output 61 md2/pa6 b parallel type: audio memory data bus lines 62 md3/pa7 b serial type: output ports 63 dv dd 5 p digital system 5.0 v power supply 64 dgnd p digital system ground 65 md4/pa8 b 66 md5/pa9 b parallel type: audio memory data bus lines 67 md6/pa10 b serial type: output ports 68 md7/pa11 b 69 wp0 o audio memory write protect output 70 r/b0 i status input that monitors audio memory 71 ale/pa4 o parallel type: audio memory address latch enable signal serial type: output ports 72 dgnd p digital system ground 73 dv dd 5 p digital system 5.0 v power supply 74 cle/pa5 o parallel type: audio memory command latch enable signal serial type: output ports 75 mwe/pa3 o parallel type: audio memory write signal serial type: output ports 76 sk/mre o parallel type: audio memory read signal serial type: audio data transfer clock 77 mcs1 o audio memory type selection (1) signal 78 mcs0 o audio memory type selection (0) signal 79 dv dd 3 p digital system 3.3 v power supply 80 dgnd p digital system ground
ps no. 6327-7/7 LC85050 this catalog provides information as of february, 2000. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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